Summary

Smart Design Environment for Digital Chips:Construction and Deployment of Design Environment in Which Students Can Tapeout Their Chip Designs

Kazutoshi KOBAYASHI 

Vol.99 No.9 pp.891-894

Publication Date:2016/09/01

Online ISSN:2188-2355

Print ISSN:0913-5693

Type of Manuscript:Special Section : Impact of VDEC on Research and Education of LSI Design ; Progress of Commodity Platform for LSI Design/Implementation in the Past 20 Years and the Next Step

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Online ISSN:2188-2355